Technical Field
The invention relates to a memory management method, and more particularly, relates to a memory management method for a rewritable non-volatile memory, a memory control circuit unit and a memory storage device using the method.
Description of Related Art
The growth of digital cameras, mobile phones, and MP3 players has been rapid in recent years. Consequently, the consumers' demand for storage media has increased tremendously. A rewritable non-volatile memory is one of the most adaptable memories for said electronic products due to its data non-volatility, low power consumption, small volume, non-mechanical structure and high read/write speed. For these reasons, the flash memory has become an import part of the electronic industries. For example, an eMMC (embedded Multi Media Card) widely adopted in mobile electronic device is one storage device that uses the flash memory as a storage medium.
Generally, the flash memory of a flash memory storage device is divided into a plurality of physical units and these physical units are grouped into a data area and a spare area. The physical units sorted into the data area are used for storing valid data written by a write command, and the physical units in the spare area are used for replacing the physical units of the data area during the execution of the write command. Specifically, when the flash memory storage device intends to perform writing for the physical units of the data area after receiving a write command from a host, the flash memory storage device retrieves one physical unit from the spare, writes to-be-written valid old data in physical units of the data area and to-be-written new data into the physical units retrieved from the spare area, associates the physical units written with the new data to the data area, and erases the physical units originally belonging to the data area and associates the same to the spare area. In order to allow the host to successfully access the physical units stored with data in an alternating manner, the flash memory storage device may provide logical units to the host. In other words, the flash memory storage device may establish a logical to physical mapping table or a physical to logical mapping table, and record and update a mapping relation between the logical unit and the physical unit in the data area to reflect the alternating (or substituting) of the physical units. As such, the host only needs to perform writing with respect to the provided logical units so the flash memory storage device can perform data reading or writing for the mapped physical units according to the logical to physical mapping table or the physical to logical mapping table.
However, as capacity and amount of the physical units become larger with advancements in manufacturing process of the flash memory, size of the mapping table and its required time for updating are increased correspondingly. To overcome said issue, a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory) is usually disposed in the flash memory storage device to serve as a cache memory. In this kind of architecture, the flash memory storage device temporarily stores said mapping table in the cache memory in order to improve overall operational efficiency of the system.
In general, if a shut down command is received by a storage device from a host system, the storage device may write aforesaid mapping tables or other system data/file for managing the storage device into the rewritable non-volatile memory of the storage device. However, after the shut down command is received by the storage device, the storage device may need to process one or more write commands before it can be really powered off. Accordingly, the previously stored mapping table or system data/file is unable to truly reflect write operations (e.g., the mapping relation updated in response to the write operation) performed after the shut down command is received. As a result, because it is possible that the previously stored mapping table and system data/file is incorrect, the storage device may enter a processing process of abnormal when the next time it is powered on, which leads to increases in the required time for powering on.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present invention. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present invention, or that any reference forms a part of the common general knowledge in the art.